View APL5620_4694737.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

APL5620
2A, Ultra Low Dropout (0.24V Typical) Linear Regulator
Features
* * * * * * * * * * * * * *
Ultra Low Dropout - 0.24V (typical) at 2A Output Current 0.8V Reference Voltage High Output Accuracy - 1.5% Over Line, Load, and Temperature Range Fast Transient Response Adjustable Output Voltage Power-On-Reset Monitoring on Both VCNTL and VIN Pins Internal Soft-Start Current-Limit and Short Current-Limit Protections Thermal Shutdown with Hysteresis Open-Drain VOUT Voltage Indicator (POK) Low Shutdown Quiescent Current ( < 30A ) Shutdown/Enable Control Function Simple TDFN3x3-10 Package with Exposed Pad Lead Free and Green Devices Available (RoHS Compliant)
General Description
The APL5620 is a 2A ultra low dropout linear regulator. The IC needs two supply voltages, one is a control voltage (V CNTL) for the control circuitry, the other is a main supply Voltage(VIN) for power conversion, to reduce power dissipation and provide extremely low dropout voltage. The APL5620 integrates many functions. A Power-On-Reset (POR) circuit monitors both supply voltages on VCNTL and VIN pins to prevent erroneous operations. The functions of thermal shutdown and current-limit protect the device against thermal and current over-loads. A POK indicates that the output voltage status with a delay time set internally. It can control other converter for power sequence. The APL5620 can be enabled by other power systems. Pulling and holding the EN voltage below 0.4V shuts off the output. The APL5620 is available in a TDFN3x3-10 package which features small size as TDFN3x3-10 and an Exposed Pad to reduce the junction-to-case resistance to extend power range of applications.
Simplified Application Circuit
VCNTL
Applications
* * *
Motherboards, VGA Cards Notebook PCs Add-in Cards
VCNTL POK POK VIN VOUT
VIN
Pin Configuration
VOUT VOUT VOUT FB POK 1 2 3 4 5 10 VCNTL 9 VIN 8 VIN 7 VIN 6 EN
VOUT
APL5620
EN EN GND FB
GND
Enable
Optional
TDFN3x3-10 (Top View) = Exposed Pad (connected to ground plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 1 www.anpec.com.tw
APL5620
Ordering and Marking Information
APL5620 Assembly Material Handling Code Temperature Range Package Code APL 5620 XXXXX Package Code QB : TDFN3x3-10 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device XXXXX - Date Code
APL5620 QB :
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
Absolute Maximum Ratings
Symbol VCNTL VIN VOUT
(Note 1)
Rating -0.3 ~ 6 -0.3 ~ 6 -0.3 ~ VIN+0.3 -0.3 ~ 7 -0.3 ~ VCNTL+0.3 Internally Limited 150 -65 ~ 150 260 V W
Parameter VCNTL Supply Voltage (VCNTL to GND) VIN Supply Voltage (VIN to GND) VOUT to GND Voltage POK to GND Voltage EN, FB to GND Voltage
Unit V V V
PD TJ TSTG TSDR
Power Dissipation Maximum Junction Temperature Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds
C C

C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol JA JC Parameter Junction-to-Ambient Resistance in Free Air
(Note 2)
Typical Value TDFN3x3-10 50 6
Unit
o
C/W C/W
Junction-to-Case Resistance in Free Air (Note 3) TDFN3x3-10
o
Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The "Thermal Pad Temperature" is measured on the PCB copper area connected to the thermal pad of package.
1 2 3 4 5
10 9 8 7 6
Measured Point PCB Copper
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
2
www.anpec.com.tw
APL5620
Recommended Operating Conditions
Symbol VCNTL VIN VOUT IOUT R2 COUT ESRCOUT TA TJ VCNTL Supply Voltage VIN Supply Voltage VOUT Output Voltage (when VCNTL-VOUT>1.7V) VOUT Output Current FB to GND IOUT = 2A at 25% nominal VOUT VOUT Output Capacitance IOUT = 1A at 25% nominal VOUT IOUT = 0.5A at 25% nominal VOUT ESR of VOUT Output Capacitor Ambient Temperature Junction Temperature Parameter Range 3.0 ~ 5.5 1.2 ~ 5.5 0.8 ~ VIN - VDROP 0~2 1k ~ 24k 8 ~ 770 8 ~ 1400 8 ~ 1700 0 ~ 200 -40 ~ 85 -40 ~ 125 m

Unit V V V A F
C C
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VCNTL=5V, vIN=1.8v, VOUT=1.2V, and TA= -40 ~ 85oC, unless otherwise specified. Typical values are at TJ=25oC. Symbol SUPPLY CURRENT IVCNTL ISD VCNTL Supply Current EN = VCNTL, IOUT=0A 1.0 20 1.5 30 1 mA A A V V V V % % %/V nA Parameter Test Conditions APL5620 Min. Typ. Max. Unit
VCNTL Supply Current at Shutdown EN = GND VIN Supply Current at Shutdown EN = GND, VIN=5.5V
POWER-ON-RESET (POR) Rising VCNTL POR Threshold VCNTL POR Hysteresis Rising VIN POR Threshold VIN POR Hysteresis OUTPUT VOLTAGE VREF Reference Voltage Output Voltage Accuracy Load Regulation Line Regulation VOUT Pull-Low Resistance FB Input Current DROPOUT VOLTAGES VOUT=2.5V VDROP VIN-to-VOUT Dropout Voltage VCNTL=4.5V, VOUT=1.8V IOUT=2A VOUT=1.2V TJ=25oC TJ=-40~125oC TJ=25 C TJ=-40~125oC TJ=25oC TJ=-40~125oC
o
2.5 0.8 FB=VOUT, IOUT=10mA, TJ=25C IOUT= 0~2A, TJ= -40~125 oC IOUT=0A ~2A IOUT=10mA, VCNTL= 3.0 ~ 5.5V VCNTL=3.3V, VEN=0V, VOUT<0.8V VFB=0.8V 0.792 -1.5 -0.15 -100 -
2.7 0.4 0.9 0.5 0.8 0.06 85 0.26 0.25 0.24 -
2.9 1.0 0.808 +1.5 0.25 +0.15 100 0.32 0.44 0.30 0.41 0.29 0.39
V
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
3
www.anpec.com.tw
APL5620
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VCNTL=5V, otherwise specified. Typical values are at TJ=25 C. Symbol PROTECTIONS ILIM ISHORT TSD Current-Limit Level Short Current-Limit Level Thermal Shutdown Temperature Thermal Shutdown Hysteresis ENABLE AND SOFT-START EN Logic High Threshold Voltage EN Hysteresis EN Pull-High Current TSS VTHPOK Soft-Start Interval Rising POK Threshold Voltage POK Threshold Hysteresis POK Pull-Low Voltage POK Denounce Interval POK Delay Time POK sinks 5mA VFBo
vIN=1.8v, VOUT=1.2V, and TA= -40 ~ 85oC, unless
APL5620 Min. Typ. Max.
Parameter
Test Conditions
Unit
3.0 2.5 0.6 -
3.6 0.8 1.6 170 50
4.3 -
A A ms
o o
C C
POWER-OK AND DELAY
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
4
www.anpec.com.tw
APL5620
Typical Operating Characteristics
4.3 4.1
Current-Limit vs. Junction Temperature
VOUT = 1.2V
900
Short Current-Limit vs. Junction Temperature
Short Current-Limit, ISHORT (mA)
850 800 750 700 650 600 550 500 -50 -25 0 25 50 75 100 125 VCNTL = 3.3V VCNTL = 5V
Current-Limit, ILIM (A)
3.9 3.7 3.5 3.3 3.1 2.9 2.7 2.5 -50 -25 0
VCNTL = 5V
VCNTL = 3.3V
25
50
75
100
125
Junction Temperature (oC)
Junction Temperature (oC)
Dropout Voltage vs. Output Current
400
400
Dropout Voltage vs. Output Current
350 300 TJ = 75X C 250 200 150 TJ = 0X C 100 50 0 TJ = - 40X C TJ = 25X C VCNTL = 3.3V VOUT = 1.2V
Dropout Voltage, VDROP (mV)
TJ = 125X C TJ = 75X C TJ = 25X C
Dropout Voltage, VDROP (mV)
350 300 250 200 150 100 50 0 0
VCNTL = 5V VOUT = 1.2V
TJ = 125X C
TJ = 0X C TJ = - 40X C
0.5
1
1.5
2
0
0.5
1
1.5
2
Output Current, IOUT (A)
Output Current, IOUT (A)
Dropout Voltage vs. Output Current
400
450
Dropout Voltage vs. Output Current
400 350 300 250 200 150 100 TJ = - 40X C 50 0 TJ = 0X C TJ = 75X C TJ = 25X C VCNTL = 3.3V VOUT = 1.5V TJ = 125X C
Dropout Voltage, VDROP (mV)
300 250 200 150 100 50 0 0 0.5 1
TJ = 125X C TJ = 75X C TJ = 25X C
TJ = 0X C TJ = - 40X C
Dropout Voltage, VDROP (mV)
350
VCNTL = 5V VOUT = 1.8V
1.5
2
0
0.5
1
1.5
2
Output Current, IOUT (A)
Output Current, IOUT (A)
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
5
www.anpec.com.tw
APL5620
Typical Operating Characteristics (Cont.)
Reference Voltage vs. Junction Temperature
0.808
VCNTL = 5V TJ = 125X C TJ = 75X C TJ = 25X C
Dropout Voltage vs. Output Current
450 400
Dropout Voltage, VDROP (mV)
350 300 250 200 150 100 50 0 0 0.5 1
Reference Voltage, VREF (V)
VOUT = 2.5V
0.806 0.804 0.802 0.800 0.798 0.796 0.794 0.792 -50
TJ = 0X C TJ = - 40X C
1.5
2
-25
0
25
50
75
100
125
Output Current, IOUT (A)
Junction Temperature (oC)
VCNTL Power Supply Rejection Ratio (PSRR)
0
0
Power Supply Rejection Ratio (dB)
VIN Power Supply Rejection Ratio (PSRR)
VCNTL=5V VIN=1.55V VINPK-PK=50mV VOUT=1.2V IOUT=2A COUT=10F
Power Supply Rejection Ratio (dB)
-10 -20 -30 -40 -50 -60 -70 -80
VCNTL=4.6~5.4V VIN=1.5V VOUT=1.2V IOUT=2A CIN=COUT=10F
-10 -20 -30 -40
1000
10000
100000
1000000
-50 100
1000
10000
100000 100000
Frequency (Hz)
Frequency (Hz)
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
6
www.anpec.com.tw
APL5620
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified.
Power On
Power Off
1
VCNTL
VCNTL 1 VIN
2
VIN 2 VOUT 3 VPOK VPOK 4
VOUT 3 4
COUT=10F, C IN=10F, R L=0.6 CH1: V CNTL , 5V/Div, DC CH2: V IN, 1V/Div, DC CH3: V OUT, 1V/Div, DC CH4: V POK, 5V/Div, DC TIME: 5ms/Div
COUT=10F, C IN=10F, R L=0.6 CH1: V CNTL , 5V/Div, DC CH2: V IN, 1V/Div, DC CH3: V OUT, 1V/Div, DC CH4: V POK, 5V/Div, DC TIME: 10ms/Div
Load Transient Response
Over Current Protection
VOUT
1 VOUT
1
IOUT
4
IOUT
4
IOUT =10mA to 2A to 10mA (rise / fall time = 1) COUT=10F, CIN=10F CH1: VOUT, 50mV/Div, AC CH4: IOUT, 1A/Div, DC TIME: 20s/Div
COUT=10F, CIN=10F, IOUT=1A to 3.4A CH1: VOUT, 1V/Div, DC CH4: IOUT, 1A/Div, DC TIME: 0.2ms/Div
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
7
www.anpec.com.tw
APL5620
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified.
Shutdown
Enable
VEN 1 VOUT
VEN 1
VOUT
2 VPOK 3 IOUT
2 VPOK 3
IOUT
4
4
COUT=10F, CIN=10F, RL=0.6 CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 5s/Div
COUT=10F, CIN=10F, RL=0.6 CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 0.5ms/Div
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
8
www.anpec.com.tw
APL5620
Pin Description
PIN NO. NAME FUNCTION Output pin of the regulator. Connecting this pin to load and output capacitors (10F at least) is required for stability and improving transient response. The output voltage is programmed by the resistor-divider connected to FB pin. The VOUT can provide 2A (max.) load current to loads. During shutdown, the output voltage is quickly discharged by an internal pull-low MOSFET. Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. Power-OK signal output pin. This pin is an open-drain output used to indicate the status of output voltage by sensing FB voltage. This pin is pulled low when output voltage is not within the Power-OK voltage window. Active-high enable control pin. Applying and holding the voltage on this pin below the enable voltage threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start process. When left this pin open, an internal pull-up current (5A typical) pulls the EN voltage and enables the regulator. Main supply input pin for voltage conversions. A decoupling capacitor (10F recommended) is usually connected near this pin to filter the voltage noise and improve transient response. The voltage on this pin is monitored for Power-On-Reset purpose Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V recommended). A decoupling capacitor (1F typical) is usually connected near this pin to filter the voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose. Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
1,2,3
VOUT
4
FB
5
POK
6
EN
7,8,9
VIN
10 Exposed Pad
VCNTL GND
Block Diagram
VCNTL
VCNTL 5A EN 0.8V POK
Thermal Shutdown
POR
Power-OnReset (POR)
Enable
Control Logic and Soft-Start Soft-Start Enable VIN
POR VREF 0.8V PWOK Delay 90% VREF
VOUT Error Amplifier
Current-Limit and Short Current-Limit
ISEN GND
FB
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
9
www.anpec.com.tw
APL5620
Typical Application Circuit
VCNTL (+5V is preferred) CCNTL 1F R3 5.1k POK 5 POK 10 VCNTL VIN VOUT APL5620 EN FB 7,8,9 1,2,3 VOUT +1.2V / 2A EN Enable 6 4 R1 12k COUT 10F (X5R/X7R Recommended) CIN 10F
VIN +1.8V
GND Exposed R2 24k Pad
C1 (Optional) (X5R/X7R Recommended)
10F: GRM31MR60J106KE19 Murata
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
10
www.anpec.com.tw
APL5620
Function Description
Power-On-Reset A Power-On-Reset (POR) circuit monitors both of supply voltages on VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after both of the supply voltages exceed their rising POR voltage thresholds during powering on. The POR function also pulls low the POK voltage regardless of the output status when one of the supply voltages falls below its falling POR voltage threshold. Internal Soft-Start An internal soft-start function controls rise rate of the output voltage to limit the current surge during start-up. The typical soft-start interval is about 0.6ms. Output Voltage Regulation An error amplifier working with a temperature-compensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from VIN to VOUT. Current-Limit Protection The APL5620 monitors the current flowing through the output NMOS and limits the maximum current to prevent load and APL5620 from damaging during current overload conditions. Short Current-Limit Protection The short current-limit function reduces the current-limit level down to 0.8A (typical) when the voltage on FB pin falls below 0.2V (typical) during current overload or shortcircuit conditions. The short current-limit function is disabled for successful start-up during soft-start. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5620. When the junction temperature exceeds +170oC, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start process after the junction temperature cools by 50oC, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown is designed with a 50oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. For normal operation, the device power dissipation should be externally limited so that junction temperatures will not exceed +125C. Enable Control The APL5620 has a dedicated enable pin (EN). A logic low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. When left open, this pin is pulled up by an internal current source (5A typical) to enable normal operation. It' not necess sary to use an external transistor to save cost. Power-OK and Delay The APL5620 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the VFB rises and reaches the rising Power-OK voltage threshold (VTHPOK), an internal delay function starts to work. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate that the output is ok. As the VFB falls and reaches the falling Power-OK voltage threshold, the IC turns on the NMOS of the POK ( after a debounce time of 10s typical ).
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
11
www.anpec.com.tw
APL5620
Application Information
Power Sequencing The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to VOUT for a long time when the main voltage applied at VIN does not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. Output Capacitor The APL5620 requires a proper output capacitor to maintain stability and improve transient response. The output capacitor selection is dependent upon ESR (equivalent series resistance) and capacitance of the output capacitor over the operating temperature. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as output capacitors. During load transients, the output capacitors which is depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the APL5620 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. Input Capacitor The APL5620 requires proper input capacitors to supply current surge during stepping load transients to prevent the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents, more parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors can all be used as an input capacitor of VIN. For most applications, the recommended input capacitance of VIN is 10F at least. However, if the drop of the input voltage is not cared, the input capacitance can be less than 10F. More capacitance reduces the variations of the supply voltage on VIN pin.
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 12 www.anpec.com.tw
Setting The Output Voltage The output voltage is programmed by the resistor divider connected to FB pin. The preset output voltage is calculated by the following equation :
R1 VOUT = 0.8 1 + R2
........... (V)
where R1 is the risistor connected from VOUT to FB with Kelvin sensing connection and R2 is the risistor connected from FB to GND. A bypass capacitor(C1) may be connected with R1 in parallel to improve load transient response and stability.
APL5620
Layout Consideration (See Figure 1)
1. Please solder the Exposed Pad on the system ground pad on the top-layer of PCBs. The ground pad must have wide size to conduct heat into the ambient air through the system ground plane and PCB as a heat sink. 2. Please place the input capacitors for VIN and VCNTL pins near the pins as close as possible for decoupling high-frequency ripples. 3. Ceramic decoupling capacitors for load must be placed near the load as close as possible for ecoupling highfrequency ripples. 4. To place APL5620 and output capacitors near the load reduces parasitic resistance and inductance for excellent load transient response. 5. The negative pins of the input and output capacitors and the GND pad must be connected to the ground plane of the load. 6. Large current paths, shown by bold lines on the figure 1, must have wide tracks. 7. Place the R1, R2, and C1 (option) near the APL5620 as close as to avoid noise coupling. 8. Connect the ground of the R2 to the GND pad by using a dedicated track. 9. Connect the one pin of the R1 to the load for Kelvin sensing. 10. Connect one pin of the C1 (option) to the VOUT pin for reliable feedback compensation.
VCNTL CCNTL VCNTL VIN APL5620 VOUT
C1 (Optional)
Thermal Consideration The TDFN3x3-10 is a cost-effective package featuring a small size and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top-layer ground plane. It is recommended to connect the top-layer ground pad to the internal ground plan by using vias. The copper of the ground plane on the top-layer conducts heat into the PCB and ambient air. Please enlarge the area of the top-layer pad and the ground plane to reduce the case-to-ambient resistance (CA).
CIN VIN VOUT COUT Load
FB GND R2 R1
Figure 1
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
13
www.anpec.com.tw
APL5620
Package Information
TDFN3x3-10
D A
E
Pin 1
D2
A1 A3
Pin 1 Corner
e S Y M B O L A A1 A3 b D D2 E E2 e L K 0.30 0.20 0.18 2.90 2.20 2.90 1.40 0.50 BSC 0.50 0.012 0.008 TDFN3x3-10 MILLIMETERS MIN. 0.70 0.00 0.20 REF 0.30 3.10 2.70 3.10 1.75 0.007 0.114 0.087 0.114 0.055 0.020 BSC 0.020 MAX. 0.80 0.05 MIN. 0.028 0.000 0.008 REF 0.012 0.122 0.106 0.122 0.069 INCHES MAX. 0.031 0.002
Note : 1. Followed from JEDEC MO-229 VEED-5.
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
14
L
E2
b
www.anpec.com.tw
APL5620
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A 330.0O .00 2
H 50 MIN. P1 8.0O .10 0
H A
T1
T1 12.4+2.00 -0.00 P2 2.0O .05 0
C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00
d 1.5 MIN. D1 1.5 MIN.
D 20.2 MIN. T 0.6+0.00 -0.40
W 12.0O .30 0 A0 3.30O .20 0
W
E1 1.75O .10 0 B0 3.30O .20 0
F 5.5O .05 0 K0 1.30O .20 0 (mm)
TDFN3x3-10
P0 4.0O .10 0
Devices Per Unit
Package Type TDFN3x3-10 Unit Tape & Reel Quantity 3000
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
15
www.anpec.com.tw
APL5620
Taping Direction Information
TDFN3x3-10
USER DIRECTION OF FEED
Classification Profile
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
16
www.anpec.com.tw
APL5620
Classification Reflow Profiles
Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time (tP)** within 5C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25C to peak temperature Sn-Pb Eutectic Assembly 100 C 150 C 60-120 seconds 3 C/second max. 183 C 60-150 seconds See Classification Temp in table 1 20** seconds 6 C/second max. 6 minutes max. Pb-Free Assembly 150 C 200 C 60-120 seconds 3C/second max. 217 C 60-150 seconds See Classification Temp in table 2 30** seconds 6 C/second max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm
3 3
Volume mm <350 235 C 220 C
3
Volume mm 350 220 C 220 C
3
Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C Volume mm 350-2000 260 C 250 C 245 C Volume mm >2000 260 C 245 C 245 C
3
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBMU2KV VMMU200V 10ms, 1trU 100mA
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
17
www.anpec.com.tw
APL5620
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2009
18
www.anpec.com.tw

▲Up To Search▲

Price & Availability of APL5620

	To Download APL5620 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .